The present disclosure relates generally to the field of shallow trench isolation structures in semiconductor substrates of integrated circuits, and, more specifically, to the field of multilayer shallow trench isolation structures in semiconductor substrates.
In very large scale integrated circuits (VLSIs), huge numbers of discrete electronic devices are present on a semiconductor substrate. Since all electronic devices are becoming miniaturized, the space between the devices is getting narrower. Due to this, isolation of the devices from each other is becoming increasingly difficult. It is common to etch shallow trenches in silicon substrates to achieve isolation of discrete electronic devices in VLSIs
However, the shallow trench isolation structures used in the art have some disadvantages. For example, voids are formed in the dielectric materials used to fill the shallow trench. Such voids formed in the dielectric materials adversely affect isolation of the devices which affects the overall structural integrity of the integrated circuits.
Accordingly, it would be desirable to provide an improved process for preparation of shallow trench isolation structures. In particular, the method should overcome the problem of void formation and provide effective device isolation.